It addresses major design methodologies with emphasis placed on structured full custom design. The course includes the study of the MOS device, critical interconnect and gate characteristics that determine the performance of VLSI circuits. It also includes CMOS logic design from transistor level schematic to layout for fabrication. Students will use state-of-the art CAD tools to verify designs and develop efficient circuit layouts.
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View larger. The authors draw upon extensive industry and classroom experience to explain modern practices of chip design. The introductory chapter covers transistor operation, CMOS gate design, fabrication, and layout at a level accessible to anyone with an elementary knowledge of digital electornics. Later chapters beuild up an in-depth discussion of the design of complex, high performance, low power CMOS Systems-on-Chip.
Download Preface. This material is protected under all copyright laws, as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher. Chapter 1 Introduction. Chapter 9 Combinational Circuit Design.
Chapter 10 Sequential Circuit Design. Chapter 13 Special-Purpose Subsystems. Chapter 14 Design Methodology and Tools. Chapter 15 Testing, Debugging, and Verification. Appendix A Hardware Description Languages. Pearson offers special pricing when you package your text with other student resources. If you're interested in creating a cost-saving package for your students, contact your Pearson rep. Cloth Package.
We're sorry! We don't recognize your username or password. Please try again. The work is protected by local and international copyright laws and is provided solely for the use of instructors in teaching their courses and assessing student learning. You have successfully signed out and will be required to sign back in should you need to download more resources. This title is out of print.
Availability This title is out of print. Overview Features Contents Order Overview. Preface Preface is available for download in PDF format. Includes modern coverage of devices, interconnect, and clocking. Provides extensive treatment of high-performance CMOS circuit design. New to This Edition. Revised introduction of designing schematics and layout for simple CMOS circuits.
Updated discussion of non-ideal transistor behaviors and their design implications. Simplified RC delay models and integration of Logical Effort as a means for designing fast circuits and estimating delay. Greater attention to leakage and low-power design. Expanded coverage of interconnect. Greater coverage of high-performance domino circuits and circuit pitfalls. Detailed coverage of modern clocking and latching techniques.
Expanded chapters on datapath and memory circuits. Unified treatment of high-performance CMOS adders. Many more worked examples illustrating important design issues. War stories of chips "gone bad" and the lessons they provide today's designers.
Historical Perspective and Pitfall sections link the theory in the text to what is happening and going wrong behind industry doors. Examples drawing on modern process technology. Two-color illustrations for improved readability. Improved exercises about 20 per chapter including many easier problems suitable for weekly problem sets.
Table of Contents Chapter 1 Introduction 1. Previous editions. Sign In We're sorry! Username Password Forgot your username or password? Sign Up Already have an access code? Instructor resource file download The work is protected by local and international copyright laws and is provided solely for the use of instructors in teaching their courses and assessing student learning.
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