It has 3 independent counters, each capable of handling clock inputs up to 10 MHz and size of each counter is 16 bit. All modes are software programmable. The is an advanced version of which did not offered the feature of read back command. It has 3 counters each with two inputs Clock and Gate and one output. Gate is used to enable or disable counting.
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The Intel and are Programmable Interval Timers PITs , which perform timing and counting functions using three bit counters. Timer Channel 2 is assigned to the PC speaker. The is described in the Intel "Component Data Catalog" publication. The , described as a superset of the with higher clock speed ratings, has a "preliminary" data sheet in the Intel "Component Data Catalog".
The is implemented in HMOS and has a "Read Back" command not available on the , and permits reading and writing of the same counter to be interleaved. Modern PC compatibles, either when using System on a Chip CPUs or discrete chipsets typically implement full compatibility for backward compatibility and interoperability. The timer has three counters, numbered 0 to 2. Once programmed, the channels operate independently. The three counters are bit down counters independent of each other, and can be easily read by the CPU.
Operation mode of the PIT is changed by setting the above hardware signals. To initialize the counters, the microprocessor must write a control word CW in this register. The control word register contains 8 bits, labeled D D0 D7 is the MSB.
The decoding is somewhat complex. Most values set the parameters for one of the three counters:. The counting process will start after the PIT has received these messages, and, in some cases, if it detects the rising edge from the GATE input signal.
Status byte format. Bit 7 allows software to monitor the current state of the OUT pin. Bit 6 indicates when the count can be read; when this bit is 1, the counting element has not yet been loaded and cannot be read back by the processor. Bits 5 through 0 are the same as the last bits written to the control register. The D3, D2, and D1 bits of the control word set the operating mode of the timer. There are 6 modes in total; for modes 2 and 3, the D3 bit is ignored, so the missing modes 6 and 7 are aliases for modes 2 and 3.
Mode 0 is used for the generation of accurate time delay under software control. In this mode, the counter will start counting from the initial COUNT value loaded into it, down to 0. Counting rate is equal to the input clock frequency. OUT remains low until the counter reaches 0, at which point OUT will be set high until the counter is reloaded or the Control Word is written. The Gate signal should remain active high for normal counting.
If Gate goes low, counting is suspended, and resumes when it goes high again. In this mode can be used as a Monostable multivibrator. GATE input is used as trigger input. OUT will be initially high. OUT will go low on the Clock pulse following a trigger to begin the one-shot pulse, and will remain low until the Counter reaches zero. After writing the Control Word and initial count, the Counter is armed.
The one-shot pulse can be repeated without rewriting the same count into the counter. If a new count is written to the Counter during a oneshot pulse, the current one-shot is not affected unless the counter is retriggered. In that case, the Counter is loaded with the new count and the oneshot pulse continues until the new count expires. In this mode, the device acts as a divide-by-n counter, which is commonly used to generate a real-time clock interrupt.
OUT will then remain high until the counter reaches 1, and will go low for one clock pulse. The following cycle, the count is reloaded, OUT goes high again, and the whole process repeats itself. The time between the high pulses depends on the preset count in the counter's register, and is calculated using the following formula:.
This mode is similar to mode 2. However, the duration of the high and low clock pulses of the output will be different from mode 2. The counter will then generate a low pulse for 1 clock cycle a strobe — after that the output will become high again. Once the device detects a rising edge on the GATE input, it will start counting.
When the counter reaches 0, the output will go low for one clock cycle — after that it will become high again, to repeat the cycle on the next rising edge of GATE. Rather, its functionality is included as part of the motherboard chipset's southbridge.
On PCs the address for timer0 chip is at port 40h.. Reprogramming typically happens during video mode changes, when the video BIOS may be executed, and during system management mode and power saving state changes, when the system BIOS may be executed. This prevents any serious alternative uses of the timer's second counter on many x86 systems. The timer that is used by the system on x86 PCs is Channel 0, and its clock ticks at a theoretical value of This is a holdover of the very first CGA PCs — they derived all necessary frequencies from a single quartz crystal , and to make TV output possible, this oscillator had to run at a multiple of the NTSC color subcarrier frequency.
As stated above, Channel 0 is implemented as a counter. The counter then resets to its initial value and begins to count down again. The fastest possible interrupt frequency is a little over a half of a megahertz.
The slowest possible frequency, which is also the one normally used by computers running MS-DOS or compatible operating systems, is about Under these real mode operating systems, the BIOS accumulates the number of INT 8 calls that it receives in real mode address c, which can be read by a program.
However, in free-running counter applications such as in the x86 PC, it is necessary to first write a latch command for the desired channel to the control register, so that both bytes read will belong to one and the same value. According to a Microsoft document, "because reads from and writes to this hardware  require communication through an IO port, programming it takes several cycles, which is prohibitively expensive for the OS.
Because of this, the aperiodic functionality is not used in practice. From Wikipedia, the free encyclopedia. Archived from the original PDF on 3 June Retrieved 26 November Godse; A.
Godse Advanced Microprocessors. Technical Publications. Intel Corporation. Archived from the original on 22 November Retrieved 21 August Archived from the original PDF on 6 December Retrieved 13 October Hidden categories: Use dmy dates from July Namespaces Article Talk. Views Read Edit View history. Contribute Help Community portal Recent changes Upload file.
D8254 - Programmable Interval Timer
Intel 8253 - Programmable Interval Timer