Up memory device using the CMOS floating gate process. The HT24LC04 is guaranteed for and each word is 8 bits. Pin Description Pin No. VSS

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Up memory device using the CMOS floating gate process. The HT24LC04 is guaranteed for and each word is 8 bits. Pin Description Pin No. VSS Note: These are stress ratings only. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil- ity. Test Conditions Symbol Parameter Min. When the write protect pin is connected to Vcc, The SCL input is used for positive edge clock data into the write protection feature is enabled and operates each EEPROM device and negative edge clock data as shown in the following table.

The A0 pin is not Device operations connected. During data transfer, the data line must remain The HT24LC04 has a write protect pin that provides stable whenever the clock line is high. Changes in hardware data protection. A read operation is initiated if this bit is high condition which must precede any other command and a write operation is initiated if this bit is low. If not, the chip will return to a standby state. This happens during the ninth following the device address word and acknowledg- clock cycle.

Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first D a ta a llo w e d to c h a n g e 8-bit data word. After receiving the 8-bit data word, the S D A EEPROM will output a zero and the addressing de- vice, such as a microcontroller, must terminate the write sequence with a stop condition. All inputs are disabled during v a lid this write cycle and EEPROM will not respond until the write is completed refer to Byte write timing.

The device address word microcontroller does not send a stop condition after consist of a mandatory one, zero sequence for the first the first data word is clocked in. These three bits microcontroller must terminate the page write se- must compare to their corresponding hard-wired input quence with a stop condition. The two device address bits must compare to their mented, retaining the memory page row location re- corresponding hardwired input pins.

The A0 pin is not fer to Page write timing. Byte write timing. Programming will be complete this feature can be used to maximize bus inhibited and the entire memory will be throughput. Once the stop condition for a write com- write-protected.

ACK polling can Read operations are initiated the same way as write be initiated immediately. If the device is still busy are three read operations: current address read, ran- with the write cycle, then no ACK will be returned. If dom address read and sequential read. The internal data word address counter maintains the last address accessed during the last read or write op- S e n d W r ite C o m m a n d eration, incremented by one.

This address stays valid between operations as long as the chip power is main- tained. The address roll over during read from the last S e n d S to p C o n d itio n to In itia te W r ite C y c le byte of the last memory page to the first byte of the first page.

The address roll over during write from the last S e n d S ta rt byte of the current page to the first byte of the same page. The microcontroller does not respond with an input zero but generates a following stop con- N o dition refer to Current read timing.

The Acknowledge polling flow microcontroller must then generate another start con- dition. The microcontroller does not respond with a zero but does generates a following stop condition refer to Random read timing. Current read timing. Random read timing. When the memory address limit is reached, the Sequential reads are initiated by either a current ad- data word address will roll over and the sequential read dress read or a random address read.

After the continues. The sequential read operation is terminated microcontroller receives a data word, it responds with an when the microcontroller does not respond with a zero acknowledgment.

As long as the EEPROM receives an but generates a following stop condition refer to Se- acknowledgment, it will continue to increment the data quential read timing. Sequential read timing. Note: The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the valid start condition of sequential command.

Holtek Semiconductor Inc. Headquarters No. Sales Office 11F, No. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as- sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise.

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HT24LC04 Datasheet PDF

General Description. Its bits of memory are organized into words. The device is optimized for use. Block Diagram.


HT24LC01-2, HT24LC02, HT24LC04



HT24LC04 PDF Datasheet浏览和下载



HT24LC04 Datasheet


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